Dual port memories typically have two ports and an array of memory cells. The memory array can be simultaneously accessed from both of the ports provided that the memory cells being accessed from one port are not the same memory cells that are being accessed from the other port. A common type of memory cell used in such dual port memories involves eight field effect transistors (FETs).
The memory cells in a single port memory typically only include six transistors. The six-transistor memory cell typically consumes only about half as much integrated circuit area as the eight-transistor cell when the two types of memory cells are fabricated using the same process. However, many application require the functionality of a dual port memory, i.e., a memory capable of handling both a read and a write operation within a single clock cycle.
In order to take advantage of the smaller size of the six-transistor memory cell, while still satisfying those applications requiring dual port memory functionality, a memory device called a pseudo-dual port memory is often used. In one example, a pseudo-dual port memory has a single memory array wherein each memory cell of the array is a six-transistor memory cell that can be selectively coupled to a single pair of bit lines (for example, bit line B and bit line bar BN).
The memory array operates as a single port memory in that only one memory access is performed at one time. The pseudo-dual port memory, however, mimics a dual port memory in that it has two ports. In one example, the pseudo-dual port memory has circuitry sometimes called a Time Delayed Multiplexer (TDM). A single input clock signal is received at the pseudo-dual port memory and this single input clock signal is used to latch an input read address, an input write address, and an input data value. The rising edge of the input clock signal is used to initiate a read operation using the input read address. The read operation is completed. Thereafter, the falling edge of the input clock signal occurs. The TDM uses the falling edge of the input clock signal to initiate a write operation. The input write address is used to address the memory array during the write operation and the data written into the memory array is the input data value. Although two memory operations are performed in a single cycle of the input clock signal, the two memory operations are in reality performed one after the other. From outside the pseudo-dual port memory, however, the pseudo-dual port memory appears to allow two accesses of the memory array at the same time or substantially at the same time, i.e., within a single clock cycle.
The amount of time required to perform the first read memory operation may not be equal to the amount of time required to perform the second write memory operation. Using a conventional TDM approach slows overall memory access times because the relative amounts of time available for the two operations is determined by the time when the rising edge of the clock cycle occurs and the time when the falling edge of the clock cycle occurs. If, for example, the clock signal is low for as long as it is high in a clock cycle (i.e., the clock signal has a 50/50 duty cycle), then the same amount of time must be allowed for performing both the faster read operation and the slower write operation. The result is an amount of wasted time that starts after the read operation has been completed and ends upon the falling edge of the clock signal.